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FPGA配置综述

上一篇 / 下一篇 2008-05-05 16:48:03 / 个人分类：学习笔记

前段时间了解了一些FPGA配置方面的知识，本文将对altera和xilinx两家的FPGA配置进行比较，总结各种配置方法并进行比较。有选择的介绍xilinx家FPGA配置流程及实现方法。

由于花费的时间不是很多，所以可能很多方面了解还不够全面，只是从我所查找到的资料显示，关于自己开发实现FPGA配置的小系统的文章多针对于altera公司的器件。而关于xilinx器件的几乎没有，有人说是因为altera公司的资源共享做得比较好，很多东西是开放的，而xilinx的相对来说提供的就没那么多，使我们想在他的现有工具基础上DIY就不那么容易，比如xilinx家的USB配置电缆买的就价值几百美金，而国内有自己DIY的altera家的USB配置电缆只要几百人民币，而且可以直接在altera的软件环境下使用。在此对这种说法不作评论，只是说关于xilinx的开发环境中如何识别它的配置硬件我还没了解到，只知道不同型号的FPGA需要不同的器件ID，而其他就不知道了！有哪位高人知道一定要和我说啊，在此先鞠躬了！！

从资料上看，关于FPGA配置方法有很多种，以Virtex系列为例，可以分为以下几种模式：

由上表可以看出，FPGA的配置模式一共有五种之多，而且，每种型号的FPGA的配置文件大小根据他的可用资源的不同而不同。但是每个型号的FPGA的配置文件始终是一样大的。每种模式需要对FPGA的模式选择脚M[2:0]设置不同的值，并且时钟情况和数据宽度也不一样。根据查到的资料，对于自己DIY配置的人来说，一般不会选择并行模式，虽然这会大大提高配置速度。下面先对这几种模式做个简单介绍，然后着重介绍一下JTAG配置的细节。

一、Configuration Process and Flow

The configuration process involves loading the configuration bitstream into the FPGA using the selected mode. There are four major phases in the configuration process:

•Clearing Configuration Memory

•Initialization

•Loading Configuration Data

•Device Startup

1、Power Up

The VCCINT power pins must be supplied with a 1.5V source.The IOB voltage input for Bank 4 (VCCO_4) and theauxiliary voltage input (VCCAUX) are also used as a logic input to the Power-On-Reset(POR) circuitry. Even if this bank is not being used, VCCO_4 must be connected to a 1.5V orgreater source.

2、Clearing Configuration Memory

In the memory clear phase, non-configuration I/O pins are 3-stated with optional pull-up resistors. The INIT_B and DONE pins are driven Low by the FPGA, and the memory is cleared. After PROG_B transitions High, memory is cleared twice and initialization can begin.

The INIT_B pin transitions High when the clearing of configuration memory is complete.

A logic Low on the PROG_B input resets the configuration logic and holds the FPGA in the clear configuration memory state. When PROG_B is released, the FPGA continues to hold INIT_B Low until it has completed clearing all of the configuration memory. The minimum Low pulse time for PROG_B is defined by the TPROGRAM timing parameter. There is no maximum value. The power-up timing of configuration signals is shown inFigure. Forcorresponding specifications。

3、Initialization

For the initialization phase, the INIT_B pin is released, the mode pins are sampled, the appropriate pins become active, and the configuration process begins. It is possible to delay configuration by externally holding INIT_B Low.

4、Delaying Configuration

The INIT_B pin can also be held Low externally to delay configuration of the FPGA. The FPGA samples its mode pins on the rising edge of INIT_B. After INIT_B transitions to High, configuration can begin. No additional time-out or waiting periods are required, but configuration does not need to commence immediately after the transition of INIT_B. The configuration logic does not begin processing data until the synchronization word from

the bitstream is loaded.

5、Loading Configuration Data

Cyclic Redundancy Checking (CRC) is automatically performedat the end of any write to the Frame. Data Input Register (FDRI), and again prior to startup. If the CRC checks do not fail, the device start-up phase can begin.

If the CRC check fails, the INIT_B pin is asserted (logic Low) to indicate that a CRC error has occurred. The startup sequence is aborted and configuration fails with DONE=0 and INIT=0.

To reconfigure the device, the PROG_B pin should be asserted to reset the configuration logic. Cycling power on the device also resets the FPGA for configuration.

6、Device Startup

Device startup brings the FPGA out of the configuration process and into normal device operation. The Startup Sequence is controlled by an eight-phase state machine that:

•Deasserts GTS, activating I/Os

•Asserts GWE, allowing RAMs and flip-flops to toggle

•Releases the DONE pin

•Asserts the End-Of-Startup signal (EOS) during the final phase. The EOS signal is an internal flag that can be read through the Status Register.

The order of the start-up events is user-programmable according to the BitGen startup options.

Delays can be inserted in the start-up sequence to allow DCMs to lock and DCI to match.

The startup sequencer always waits for the DONE pin on the FPGA to go High during the Done cycle. The DONE pin does not necessarily go High when it is "released" by the device, since the pin may be held Low externally by other devices. The DONE pin can be configured as an open-drain output, in which case the DONE pin is "released" to a high-impedance state. Alternatively, it can be configured as an active driver, in which case the DONE pin is "released" to an active High level. The BitGen DRIVE DONE (bitgen-g drivedone:yes) setting determines whether the active driver is enabled on the DONE pin. This feature allows several FPGAs with connected DONE pins become active simultaneously.

二、五种配置模式的简要介绍

1、Serial Programming Modes

In the serial programming modes, the FPGA is configured by loading one bit per CCLK cycle. In Master Serial mode, the FPGA drives the CCLK pin. In Slave Serial mode, the FPGAs CCLK pin is driven by an external source. In both serial configuration modes, the MSB of each data byte is always written to the DIN pin first.

Master Serial Mode

The Master Serial mode is designed so the FPGA can be configured from a Serial PROM.

Slave Serial Mode

In serial configuration mode, the FPGA is configured by loading one bit per CCLK cycle. In Slave Serial mode, the FPGAs CCLK pin is driven by an external source. In both serial configuration modes, the MSB of each data byte is always written to the DIN pin first.The Slave Serial configuration mode allows for FPGAs to be configured from other logic devices, such as microprocessors, or in a daisy-chain fashion.

2、SelectMAP Programming Modes

The SelectMAP™ interface provides an 8-bit bidirectional data bus interface to the Virtex-II configuration logic. In Master SelectMAP mode the CCLK signal is an output from the FPGA. In Slave SelectMAP mode the CCLK signal is an input. Slave SelectMAP mode allows for both configuration and readback, while only configuration is possible in Master SelectMAP mode.

Master SelectMAP Mode

Slave SelectMAP Mode

3、1、JTAGConfiguration Pins

Dedicated pins (CCLK, PROG_B, DONE, M2, M1, and M0) powered by VCCAUX aredesignated for configuration. Dual-function pins (D0/DIN, D1:D7, CS_B, RDWR_B, BUSY/DOUT and INIT_B) powered by VCCO are designated for configuration and other user functions after configuration.

Before and during configuration, all configuration I/O pins are set for LVTTL, 12mA,fastslew rate, except for the CCLK pin. It is set for LVTTL, 12mA,slowslew rate.

5、2、JTAG Configuration Mode

For JTAG configuration mode, JTAG inputs are independent of VCCO and work between 2.5V and 3.3V TTL levels (VIL max = .8V, VIH min = 2.0V). The JTAG input pins are 3.3V tolerant. The JTAG output (TDO) is an active driver.

JTAG / Boundary Scan Programming Mode

Introduction

Virtex-II devices support the new IEEE 1532 standard for In-System Configuration (ISC),based on the IEEE 1149.1 standard. The IEEE 1149.1 Test Access Port and Boundary-Scan Architecture is commonly referred to as JTAG.

JTAG is an acronym for the Joint Test Action Group, the technical subcommittee initially responsible for developing the standard. This

standard provides a means to assure the integrity of individual components and the interconnections between them at the board level. With increasingly dense multi-layer PC boards, and more sophisticated surface mounting techniques, boundary-scan testing is becoming widely used as an important debugging standard.

Devices containing boundary-scan logic can send data out on I/O pins in order to test connections between devices at the board level. The circuitry can also be used to send signals internally to test the device specific behavior. These tests are commonly used to detect opens and shorts at both the board and device level.

In addition to testing, boundary-scan offers the flexibility for a device to have its own set of user-defined instructions. The added common vendor-specific instructions, such as configure and verify, have increased the popularity of boundary-scan testing and functionality.

There are three input pins and one output pin to control the 1149.1 boundary-scan TAP controller. There are optional control pins, such as TRST (Test Reset) and enable pins,which might be found on devices from other manufacturers. It is important to be aware of these optional signals when interfacing Xilinx devices with parts from different vendors, because they might need to be driven.

pins are outlined below.

•TMS - This pin determines the sequence of states through the TAP controller on the rising edge of TCK. TMS has an internal resistive pull-up to provide a logic High if the pin is not driven.

•TCK - This pin is the JTAG test clock. It sequences the TAP controller and the JTAG registers in the Virtex-II devices.

•TDI - This pin is the serial input to all JTAG instruction and data registers. The state of the TAP controller and the current instruction held in the instruction register determine which register is fed by the TDI pin for a specific operation. TDI has an internal resistive pull-up to provide a logic High to the system if the pin is not driven.TDI is applied into the JTAG registers on the rising edge of TCK.

•TDO - This pin is the serial output for all JTAG instruction and data registers. The state of the TAP controller and the current instruction held in the instruction register determine which register (instruction or data) feeds TDO for a specific operation.

TDO changes state on the falling edge of TCK and is only active during the shifting of instructions or data through the device. This pin is 3-stated at all other times.

NOTE:As specified by the IEEE Standard, the TMS and TDI pins all have internal pull-up resistors by default. These internal pull-up resistors of 50-150 kΩare active, regardless of the mode selected. User can select a pull-up, pull-down, or float option in the implementation tools.

diagrams a 16-state finite state machine. The four TAP pins control how data is scanned into the various registers. The state of the TMS pin at the rising edge of TCK determines the sequence of state transitions. There are two main sequences, one for shifting data into the data register and the other for shifting an instruction into theinstruction register.

5、3、Boundary-Scan Instruction Set

To determine the operation to be invoked, an instruction is loaded into the Instruction Register (IR). The Instruction Register is 6 bits long in Virtex-II devices to support the new IEEE Standard 1532 for In-System Configurable (ISC) devices.