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			    <title>Bachelor Hall</title>
			    <link>http://www.edacn.net/?uid-82392</link>
			    <description></description>
			    <copyright>Copyright(C) Bachelor Hall</copyright>
			    <generator>SupeSite/X-Space</generator>
			    <lastBuildDate>Sun, 23 Nov 2008 00:22:37 GMT</lastBuildDate><item>
								<title>抱歉</title>
								<link>http://www.edacn.net/?uid-82392-action-viewspace-itemid-7563</link>
								<description><![CDATA[抱歉的很，因为现在在公司实习，作为研发一般是无法上网的，等自己有了电脑才能继续了。]]></description>
								<category>blog</category>
								<author>霡霂</author>
								<pubDate>Sat, 30 Jun 2007 14:41:32 GMT</pubDate>
							</item>
							<item>
								<title>三段式状态机</title>
								<link>http://www.edacn.net/?uid-82392-action-viewspace-itemid-7562</link>
								<description><![CDATA[<P class=MsoNormal style="MARGIN: 4pt 0cm 0pt; TEXT-INDENT: 21pt; LINE-HEIGHT: 16pt; mso-line-height-rule: exactly"><SPAN style="FONT-FAMILY: 宋体; mso-ascii-font-family: "><FONT face=arial,helvetica,sans-serif size=2>时序电路的状态是一个状态变量集合，...]]></description>
								<category>blog</category>
								<author>霡霂</author>
								<pubDate>Sat, 30 Jun 2007 14:36:50 GMT</pubDate>
							</item>
							<item>
								<title>汉明码的原理</title>
								<link>http://www.edacn.net/?uid-82392-action-viewspace-itemid-7561</link>
								<description><![CDATA[<P style="MARGIN-LEFT: 0px; LINE-HEIGHT: 150%; MARGIN-RIGHT: 0px; TEXT-ALIGN: center" align=center><IMG height=149 src="http://www.stor-age.com/resources/2A16DE5E-C349-4474-918A-E5A5428620AF/ecc.gif" width=435 border=1></P>
<P style="MARGIN-LEFT: 0px;...]]></description>
								<category>blog</category>
								<author>霡霂</author>
								<pubDate>Sat, 30 Jun 2007 14:35:36 GMT</pubDate>
							</item>
							<item>
								<title>基于ActiveHDL的StateMachine设计</title>
								<link>http://www.edacn.net/?uid-82392-action-viewspace-itemid-7559</link>
								<description><![CDATA[<P>1.新建 empty workspace</P>
<P>2.新建 new state diagram</P>
<P>3.增加input 端口 命名为reset</P>
<P>4.右键选择state machine 设置clock,clock enable,reset</P>
<P>5.增加状态</P>]]></description>
								<category>blog</category>
								<author>霡霂</author>
								<pubDate>Sat, 30 Jun 2007 13:41:16 GMT</pubDate>
							</item>
							<item>
								<title>状态机的一种书写方式</title>
								<link>http://www.edacn.net/?uid-82392-action-viewspace-itemid-7558</link>
								<description><![CDATA[<BR>`define S1 0<BR>`define S2 1<BR>`define S3 2<BR>`define S4 3<BR>`define S5 4<BR>`define S6 5<BR>`define S7 6<BR>`define S8 7<BR>module clk_gen2 (clk,reset,clk1,clk2,clk4,fetch,alu_clk);<BR>input clk,reset;<BR>output clk1,clk2,clk4,fetch,alu_clk;<BR...]]></description>
								<category>blog</category>
								<author>霡霂</author>
								<pubDate>Sat, 30 Jun 2007 13:35:20 GMT</pubDate>
							</item>
							<item>
								<title>Verilog的打印系统函数</title>
								<link>http://www.edacn.net/?uid-82392-action-viewspace-itemid-7557</link>
								<description><![CDATA[<P>Verilog本质上也是一门高级语言，因而也提供了丰富打印信息、输出信息的系统函数。<BR>Verilog提供的打印系统函数分为三类：<BR>显示/写系统函数(Display and Write tasks)<BR>脉冲选择监视系统函数(strobed monitoring tasks)<BR>连续监视系统函数(continuous monitor...]]></description>
								<category>blog</category>
								<author>霡霂</author>
								<pubDate>Sat, 30 Jun 2007 13:19:42 GMT</pubDate>
							</item>
							<item>
								<title>真正爱你的女孩</title>
								<link>http://www.edacn.net/?uid-82392-action-viewspace-itemid-7556</link>
								<description><![CDATA[<P>　　1.真正爱你的女孩，在别人面前总是野蛮，只会为你温柔，眼泪特别多.</P>
<P>　　2.真正爱你的女孩，总是会对你说别抽烟，尽管她知道你改不了，还是不耐烦的说.</P>
<P>　　3.真正爱你的女孩，无时无刻都想知道你在干什么.</P>
<P>　　4.真正爱你的女孩，会为你晚...]]></description>
								<category>blog</category>
								<author>霡霂</author>
								<pubDate>Sat, 30 Jun 2007 13:16:30 GMT</pubDate>
							</item>
							<item>
								<title>modlesim教学(繁体版)</title>
								<link>http://www.edacn.net/?uid-82392-action-viewspace-itemid-7555</link>
								<description><![CDATA[<TABLE width="95%" border=0>
<TBODY>
<TR>
<TD width="100%">
<P style="LINE-HEIGHT: 130%"><FONT size=2><SPAN style="LETTER-SPACING: 1px"><B>準備事項</B></SPAN></FONT></P>
<OL>
<LI>
<P style="LINE-HEIGHT: 130%"><FONT size=2><SPAN style="LETTER-SPA...]]></description>
								<category>blog</category>
								<author>霡霂</author>
								<pubDate>Sat, 30 Jun 2007 08:59:09 GMT</pubDate>
							</item>
							<item>
								<title>LVDS技术原理和设计简介</title>
								<link>http://www.edacn.net/?uid-82392-action-viewspace-itemid-2625</link>
								<description><![CDATA[<P>摘 要： 介绍了LVDS（低电压差分信号）技术的原理和应用，并讨论了在单板和系统设计中应用LVDS时的布线技巧。</P>
<P>&nbsp;&nbsp;&nbsp; 关键词： LVDS PCB设计</P>
<P><B>１ LVDS介绍</B></P>
<P>&nbsp;&nbsp;&nbsp; LVDS（Low Voltage Differential Signaling)是...]]></description>
								<category>blog</category>
								<author>霡霂</author>
								<pubDate>Tue, 19 Sep 2006 13:25:27 GMT</pubDate>
							</item>
							<item>
								<title>逻辑状态</title>
								<link>http://www.edacn.net/?uid-82392-action-viewspace-itemid-2624</link>
								<description><![CDATA[<P>两态:0,1</P>
<P>三态:0,1,x</P>
<P>四态:0,1,x,z</P>
<P>九态:U,X,0,1,Z,W,L,H,-</P>
<P>对九态的解释:</P>
<P>U:初始态<BR>X:不定态<BR>0:0<BR>1:1<BR>Z:高阻态<BR>W:弱信号不定态<BR>L:弱信号0<BR>H:弱信号1<BR>-:不可能态</P>]]></description>
								<category>blog</category>
								<author>霡霂</author>
								<pubDate>Thu, 07 Sep 2006 22:00:42 GMT</pubDate>
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