状态机的一种书写方式

`define S1 0EDA中国门户网站+z%ZM"P:c!P1W7a$E
`define S2 1EDA中国门户网站/u#?`.qlH0g
`define S3 2
5{(P*L)`(F17814`define S4 3
0I2CqA-X%K*s17814`define S5 4EDA中国门户网站qH_ZqX7iy+_8w/m
`define S6 5
\1f5r+U9c Q3s]^@H17814`define S7 6
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mq17814`define S8 7

module clk_gen2 (clk,reset,clk1,clk2,clk4,fetch,alu_clk);

input clk,reset;
g'T ~Qz8N8{7g6i17814output clk1,clk2,clk4,fetch,alu_clk;

wire clk,reset;EDA中国门户网站}*a3HV*jM&?-v
reg clk2,clk4,fetch,alu_clk;EDA中国门户网站h
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reg[7:0] state,next_state;

wire s_s1 = state[`S1];EDA中国门户网站7j2}0Unq7z1]|
wire s_s2 = state[`S2];
W(D!udE,TC17814wire s_s3 = state[`S3];
U6f{:Ma6Lo`17814wire s_s4 = state[`S4];
u3EWW"m.hr~m`17814wire s_s5 = state[`S5];EDA中国门户网站4kS H pU(~
wire s_s6 = state[`S6];EDA中国门户网站.`NrV7j*Xt
wire s_s7 = state[`S7];
3oB,p.B-G17814wire s_s8 = state[`S8];

assign clk1 = ~clk;

//----------------------状态机-----------------
\lVyR XC7G17814//状态机的时序逻辑EDA中国门户网站:S(H5W9jE8l[)C
always @(negedge clk)EDA中国门户网站 TSnP1Su&K^
state <= next_state;

//状态机的组合逻辑（可能没有实际的组合电路），仅表示状态跳转，EDA中国门户网站
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//增强代码的可读性EDA中国门户网站.^#YP'VM\]Ui%F
//既然是时钟发生器，最好不要用reset，否则复位将导致时钟中断，EDA中国门户网站8p6NM7n2J?G3o&B jZW/Q*H
//特别时钟要输出给其它模块或其它游器件用的时候EDA中国门户网站{C:z1Y%T4C.Lz
always @(state)
VLw:Y:{+Iq17814begin
1Hb|,wn17814next_state = 8'b0000_0000;

case(1'b1)EDA中国门户网站a6E$M1C_"z+d
state[`S1] : next_state[`S2] = 1'b1;EDA中国门户网站9M,N VZ}0?%B
state[`S2] : next_state[`S3] = 1'b1;
f2l%|m(n.`M17814state[`S3] : next_state[`S4] = 1'b1;EDA中国门户网站4R#\x.N4xNE
state[`S4] : next_state[`S5] = 1'b1;
{6g`,kJ4hx3i17814state[`S5] : next_state[`S6] = 1'b1;EDA中国门户网站
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state[`S6] : next_state[`S7] = 1'b1;
(UK e)B jd?qS6i17814state[`S7] : next_state[`S8] = 1'b1;EDA中国门户网站9OGO+M,i UuE
state[`S8] : next_state[`S1] = 1'b1;
*}8gji'T8gV9FkG17814default : next_state[`S1] = 1'b1;EDA中国门户网站
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endcase
'j8l8i:p d4?k17814end

//-----------------处理逻辑-------------------------EDA中国门户网站9T cwg4sZ
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always @(negedge clk)
'AI)}8wKSr[*eL+k_o17814clk2 <= ~clk2;

always @(negedge clk)EDA中国门户网站9{o-U;@PE0`
if (s_s1 | s_s2)EDA中国门户网站:Z/X.{)`#wpJ%g1J
alu_clk <= ~alu_clk;

always @(negedge clk)EDA中国门户网站n?.tw
NE _
if (s_s2 | s_s4 | s_s6 | s_s8)EDA中国门户网站/|B@s yYP?j
clk4 <= ~clk4;

always @(negedge clk)
|A+_VT7r5ix-k _17814if (s_s4 | s_s8)EDA中国门户网站,]&X
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fetch <= ~fetch;

endmodule