悬赏主题
求格雷码转二进制的Verilog代码补充资料做了半天做不对..烦躁啊 8位格雷 转8位二进制注 需要可综合的 希望不是组合逻辑 时钟上升沿完成转换 always @ ( posedge Wr_Clk_307p2MHz or posedge Reset ) begin: Loop integer i; if ( Reset == 1 ) Temp_Rd_Ptr_Bin = 8'b00000000; else begin Temp_Rd_Ptr_Bin[7] = Temp_Rd_Ptr_Gray[7]; for ( i=7; i>0; i=i-1 ) Temp_Rd_Ptr_Bin[i-1] = Temp_Rd_Ptr_Bin ^ Temp_Rd_Ptr_Gray[i-1]; end end 自己写的 但是不知道在时序电路中使用阻塞赋值会不会有什么问题 但是非阻塞赋值是会得出错误的结果 [ 本帖最后由 almer 于 2008-8-6 10:08 编辑 ]
最佳答案 ( 回答者: cryinrain_cug )
module Grey2Bin ( BinCode, GreyCode, Enable, Clk, Reset_b);
// I/O define output [7:0] BinCode ; input [7:0] GreyCode; input Enable ; input Clk ; input Reset_b ; reg [7:0] BinCode ; wire [7:0] GreyCode; wire Enable; wire Clk; wire Reset_b; // function always @ (posedge Clk) begin if (!Reset_b) BinCode <= 8'h00; else begin if (Enable) begin BinCode [7] <= GreyCode [7]; @ (posedge Clk) BinCode [6] <= (GreyCode [6] ^ BinCode [7] ); @ (posedge Clk) BinCode [5] <= (GreyCode [5] ^ BinCode [6] ); @ (posedge Clk) BinCode [4] <= (GreyCode [4] ^ BinCode [5] ); @ (posedge Clk) BinCode [3] <= (GreyCode [3] ^ BinCode [4] ); @ (posedge Clk) BinCode [2] <= (GreyCode [2] ^ BinCode [3] ); @ (posedge Clk) BinCode [1] <= (GreyCode [1] ^ BinCode [2] ); @ (posedge Clk) BinCode [0] <= (GreyCode [0] ^ BinCode [1] ); end else BinCode <= 8'h00; end end endmodule lz试试这个.可以综合.仿真你试试看看  |
|
|
|
